K4X51163PC-FGC3 (SAM) - 32M x16 Mobile-DDR SDRAM ic in stock 30,000 hot price
Description
| Supply Ability: | 30,000 Piece/Pieces per Month |
| Minimum Order Quantity: | 100 Piece/Pieces |
| Payment Terms: | T/T |
Product Details
FEATURES
1.8V power supply, 1.8V I/O power
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Four banks operation
1 /CS
1 CKE
Differential clock inputs(CK and CK)
MRS cycle with address key programs
- CAS Latency ( 2, 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
Internal Temperature Compensated Self Refresh
Deep Power Down Mode
All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
Data I/O transactions on both edges of data strobe, DM for masking.
Edge aligned data output, center aligned data input.
No DLL; CK to DQS is not synchronized.
LDM, UDM for write masking only.
Auto refresh duty cycle
- 7.8us for -25 to 85